1. Field of the Invention
The present invention relates to a complex multiplexer/demultiplexer apparatus, more particularly relates to a multiplexer/demultiplexer apparatus which converts low order group data signals to middle order group data signals to multiplex high order group data signals and converts high order group data signals to middle order group data signals to demultiplex low order data signals.
Telecommunications multiplexer/demultiplexer apparatuses used for exchange systems etc. are able to multiplex a plurality of low order group data signals to obtain a high order group data signal and to demultiplex a high order group data signal to obtain a plurality of low order group data signals.
Here, low order group data signals mean, for example, first order group data signals, while middle order group data signals and high order group data signals mean, respectively, for example, second order group data signals and third order group data signals.
2. Description of the Prior Art
As explained in detail later, in the conventional complex multiplexer/demultiplexer apparatuses (hereinafter simply referred to as MUX/DEMUX apparatuses), in the multiplexer part, the clocks used by the first multiplexer units for performing multiplexing from low order groups to middle order groups, for example, seven first multiplexer units corresponding to seven channels, were supplied individually from a second multiplexer unit which performed multiplexing of middle order groups to high order groups. The same was true in the demultiplexer part. The timing clocks used by the second demultiplexer units performing multiplexing from middle order groups to low order groups, for example, seven second demultiplexer units corresponding to seven channels, were supplied independently from the first demultiplexer units performing demultiplexing from high order groups to middle order groups.
Therefore, while there were demands for making conventional multiplexer/demultiplexer apparatuses by a plurality of LSI's (large scale integrated circuits), there was a problem in that they could not be easily constructed by LSI's. The reason was that the number of input/output pins of individual LSI's is fixed and if the number of input/output pins required for inputting and outputting seven channels worth of timing clocks increased, the number of input/output pins for the inherent multiplexing/demultiplexing data processing would end up reduced.